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C8051F380/1/2/3/4/5/6/7/C
USB Register Definition 21.19. EENABLE: USB0 Endpoint Enable
Bit
7
6
5
4
3
2
1
0
Name
EEN3
EEN2
EEN1
Type
Reset
R
1
R
1
R
1
R
1
R/W
1
R/W
1
R/W
1
R/W
1
USB Register Address = 0x1E
Bit Name
Function
7:4
3
2
1
0
Unused
EEN3
EEN2
EEN1
Reserved
Read = 1111b. Write = don’t care.
Endpoint 3 Enable.
This bit enables/disables Endpoint 3.
0: Endpoint 3 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 3 is enabled (normal).
Endpoint 2 Enable.
This bit enables/disables Endpoint 2.
0: Endpoint 2 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 2 is enabled (normal).
Endpoint 1 Enable.
This bit enables/disables Endpoint 1.
0: Endpoint 1 is disabled (no NACK, ACK, or STALL on the USB network).
1: Endpoint 1 is enabled (normal).
Must Write 1b.
21.12. Controlling Endpoints1-3 IN
Endpoints1-3 IN are managed via USB registers EINCSRL and EINCSRH. All IN endpoints can be used
for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing 1 to the ISO bit
in register EINCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 IN interrupt is generated by any of the following conditions:
1. An IN packet is successfully transferred to the host.
2. Software writes 1 to the FLUSH bit (EINCSRL.3) when the target FIFO is not empty.
3. Hardware generates a STALL condition.
21.12.1. Endpoints1-3 IN Interrupt or Bulk Mode
When the ISO bit (EINCSRH.6) = 0 the target endpoint operates in Bulk or Interrupt Mode. Once an end-
point has been configured to operate in Bulk/Interrupt IN mode (typically following an Endpoint0 SET_IN-
TERFACE command), firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY
bit (EINCSRL.0). Upon reception of an IN token, hardware will transmit the data, clear the INPRDY bit, and
generate an interrupt.
Writing 1 to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be
transmitted upon reception of the next IN token.
Rev. 1.4
197
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